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MITSUBISHI LSIsLSIs MITSUBISHI
M5M4V4405CJ,TP-6,-7,-6S,-7S M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (1048576-WORD BY BY 4-BIT) DYNAMIC RAM EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD 4-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1 DQ2 2 W3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
FEATURES
Type name
M5M4V4405CXX-6, -6S M5M4V4405CXX-7, -7S
A0 9 RAS CAS Address OE Cycle Power dissipaaccess access access access tion time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW) A1 10 A2 11 A3 12 VCC 13
18 A8 17 A7 16 A6 15 A5 14 A4
60 70
15 20
30 35
15 20
110 130
264 231
XX=J, TP
Standard 26 pin SOJ, 26 pin TSOP(II) Single 3.3V0.3V supply Low stand-by power dissipation CMOS lnput level .................................................1.8mW(Max)* CMOS lnput level ................................................180W(Max) Low operating power dissipation M5M4V4405Cxx-6, -6S .....................................288.0mW (Max) M5M4V4405Cxx-7, -7S ....................................252.0mW (Max) Self refresh capabiility* Self refresh current ..............................................100A(max) Extended refresh capability* Extended refresh current ....................................100A(max) Hyper-page mode (1024-bit random access), Read-modify- write, RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR self refresh(-6S,-7S) capabilities. Early-write mode and OE and W to control output buffer impedance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every128ms (A0~A9)* *: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S: option) only
Outline 26P0J (300mil SOJ)
DQ1 1 DQ2 2 W3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
A0 9 A1 10 A2 11 A3 12 VCC 13
18 A8 17 A7 16 A6 15 A5 14 A4
APPLICATION
Lap top personal computer,Solid state disc, Microcomputer memory, Refresh memory for CRT
Outline 26P3Z-E (300mil TSOP)
PIN DESCRIPTION
Pin name A0~A9 DQ1~DQ4 RAS CAS W OE VCC VSS Function Address inputs Data inputs / outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+3.3V) Ground (0V)
1
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations the M5M4V4405CJ,TP provide, a number of other functions, e.g., Hyper Page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs Operation RAS Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Self refresh* Stand-by ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC DNC NAC NAC DNC OE ACT DNC NAC ACT DNC ACT DNC DNC DNC Row Column address address APD APD APD APD APD DNC DNC DNC DNC APD APD AP D APD DNC DNC DNC DNC DNC Input/Output Refresh Input OPN APD APD APD DNC OPN DNC DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN OPN YES YES YES YES YES YES YES YES NO Hyper Page mode identical Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT W A0 ~ A9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
VCC (3.3V)
CLOCK GENERATOR CIRCUIT
VSS (0V)
COLUMN DECODER
(4) DATA IN BUFFERS DQ1 DQ2 DQ3 DQ4 (4) DATA OUT BUFFERS OUTPUT OE ENABLE INPUT DATA INPUTS / OUTPUTS
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER ROW A0~ A9 DECODER
SENSE REFRESH AMPLIFER & I /O CONTROL
MEMORY CELL (4,194,304 BITS)
2
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to VSS Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 0 ~ 70 -65 ~ 150 Unit V V V mA mW C C
Ta=25 C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C, unless otherwise noted)
Symbol VCC VSS VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs DQ1~DQ4 Low-level input voltage others Min 3.0 0 2.0 -0.3 -0.3 Limits Nom 3.3 0 Max 3.6 0
VCC+0.3
(Note 1)
Unit V V V V V
0.8 0.8
Note 1 : All voltage values are with respect to VSS.
ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC=3.3V 0.3V, VsS=0V, unless otherwise noted)
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from VCC operating (Note 3,4,5) Supply current from VcC , stand-by (Note 6) Average supply current from VCC refreshing (Note 3,5) Average supply current from VCC Hyper-Page-Mode (Note 3,4,5) Average supply current from VCC, CAS before RAS refresh mode (Note 3)
M5M4V4405C-6,-6S
(Note 2)
Test conditions IOH=-2mA IOL=2mA Q floating, 0VVOUTVCC
0VVINVCC+0.3V, Other inputs pins=0V
Min 2.4 0 -5 -5
Limits Typ
Max Vcc 0.4 5 5 80
Unit V V A A mA
RAS, CAS cycling tRC=tWC=min. M5M4V4405C-7,-7S output open RAS=CAS =VIH, output open
M5M4V4405C M5M4V4405C(S)
70 2 0.5 0.05 * 80 mA 70 80 70 70 mA 60 mA mA
ICC2 (AV)
RAS=CASVCC -0.2V output open
M5M4V4405C-6,-6S RAS cycling, CAS= VIH
ICC3 (AV)
tRC=min. M5M4V4405C-7,-7S output open
M5M4V4405C-6,-6S RAS=VIL, CAS cycling
ICC4(AV)
tPC=min. M5M4V4405C-7,-7S output open
M5M4V4405C-6,-6S CAS before RAS refresh cycling
ICC6(AV)
tRC=min. M5M4V4405C-7,-7S output open RAS cycling CAS0.2V or CAS before RAS refresh cycling RAS0.2V or VCC-0.2V CAS0.2V or VCC-0.2V W0.2V (Except for RAS falling edge) or VCC-0.2V OE0.2V or VCC-0.2V A0~A9 0.2V orVCC-0.2V DQ=open tRC=125s, tRAS=tRAS min ~1s RAS=CAS0.2V output open
ICC8(AV)*
Average supply current from VCC Extended-Refresh cycle
100
A
(Note 6)
ICC9(AV)*
Average supply current from VCC Self-Refresh cycle (Note 6)
M5M4V4405C(S)
100
A
3
Note 2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Addres can be changed once or less while RAS=VIL and CAS=VIH.
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70C, VCC=3.3V0.3V, Vss=0V, unless otherwise noted)
Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Min Limits Typ Max 5 7 7 Unit pF pF pF
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC=3.3V0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Parameter Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output hold time from CAS Output hold time from RAS Output low impedance time from CAS low Output disable time after OE high Output disable time after WE low Output disable time after CAS high Output disable time after RAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13) 5 5 5 15 15 15 15 Limits A@
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 15 60 30 33 15
Min
Max 20 70 35 38 20
5 5 5 20 20 20 20
Note 6: An initial pause of 200s is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh cycles)ADA@A@A@A@A@A@A@A@A@A@A@A@A@ A@ Note the RAS may be cycled during the initial pause. And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 100pF, VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=2mA). The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCDtRCD(max) and tASCtASC(max) and tCPtCP(max). 9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRADtRAD(max) and tASCtASC(max). 11: Assumes that tCPtCP(max) and tASCtASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state(IOUT | 10A |) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high.
4
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70C, VCC = 3.3V0.3V, VSS =0V, unless otherwise noted, see notes 14,15) Limits Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Parameter Refresh cycle time Refresh cycle time* RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, RAS high to data Delay time, CAS high to data Delay time, OE high to data Transition time
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 16.4 128
Min
Max 16.4 128 50
(Note 16)
(Note 17) (Note 18)
(Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 21)
40 20 5 0 10 15 0 0 10 10 0 0 15 15 15 1
50 45 20 5 0 13 15 0 0 10 10 0 0 20 20 20 1
30 13
35 13
50
50
Note 14: The timing requirements are assumed tT =2ns. A@ 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. A@ 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. A@ 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. A@ 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. A@ 19: Either tDZC or tDZO must be satisfied. A@ 20: Either tRDD or tCDD or tODD must be satisfied. A@ 21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time Parameter
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22) (Note 22)
Min 110 60 10 48 15 0 0 0 30 18 15 15
Max 10000 10000
Min 130 70 13 55 20 0 0 0 35 23 20 20
Max 10000 10000
5
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low Parameter
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
(Note 24)
Min 110 60 10 48 10 0 10 10 10 10 0 10
Max 10000 10000
Min 130 70 13 55 13 0 13 13 13 13 0 13
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before0 CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low OE hold time after W low (Note 23)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns
(Note 24) (Note 24) (Note 24)
Min 133 89 44 89 44 0 32 77 47 15
Max 10000 10000
Min 161 107 57 107 57 0 42 92 57 20
Max 10000 10000
Note 23: tRWC is specified as tRWC(min )=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. A@ 24: tWCS, tCWD, tRWD, tAWD, and tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. IftCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD (min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
6
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W)
Limits Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time Hyper Page Mode read write / read modify write cycle time Output hold time from CAS low RAS low pulse width for read or write cycle CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low Hold time to maintain the data Hi-Z until CAS access OE Pulse Width (Hi-Z control) W Pulse Width (Hi-Z control) Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read (Note 26)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
(Note 25)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min 25 66 5 77 10 33 50 7 7 7 32 47 50 15 30 33
Max
Min 30 79 5 92 13 38 60 7 7 7 42 57 60 20 35 38
Max
(Note 27) (Note 28) (Note 24)
100000 16
100000 16
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tHPC(min) is specified in the case of read-only and early write-only in Hyper page Mode. 27: tRAS(min) is specified as two cycles of CAS input are performed. 28: tCP(max)) is specified as a reference point only.
CAS before RAS Refresh Cycle
Symbol tCSR tCHR tRSR tRHP tCAS
(Note 29)
Limits Parameter CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low CAS low pulse width
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns
Min 5 10 10 10 17
Max
Min 5 15 10 15 22
Max
Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle* (Note 30)
Limits Symbol tRASS tRPS tCHS tRSR tRHR Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time Read setup time before RAS low Read hold time after RAS low
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit s ns ns ns ns
Min 100 110 -50 10 10
Max
Min 100 130 -50 10 15
Max
7
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Test Mode Specification (Note 31) ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC=3.3V0.3V, VSS=0V, unless otherwise noted) (Note 2)
Symbol ICC1 (AV) Parameter Average supply current from VCC operating (Note 3,4,5) Average supply current from VCC refreshing (Note 3,5) Average supply current from VCC Hyper-Page-Mode (Note 3,4,5) Average supply current from VCC CAS before RAS refresh (Note 3) mode
M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Test conditions RAS, CAS cycling tRC=tWC=min. output open RAS cycling, CAS= VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open
Min
Limits Typ
Max 85 75 85 75 85 75 75
Unit mA
ICC3 (AV)
mA
ICC4(AV)
mA
ICC6(AV)
mA 65
Note 31: All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode.
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC=3.3V0.3V, VSS=0V, unless otherwise noted, see notes 6,14,15)
Limits Symbol tCAC tRAC tAA tCPA tOEA Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Parameter (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns
Min
Max 20 65 35 38 20
Min
Max 25 75 40 43 25
TIMING REQUIREMENTS (Ta=0~70C, VCC=3.3V0.3V, VSS=0V, unless otherwise noted, see notes 14,15) Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRAL tCAL tORH tOCH Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low Parameter
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns
Min 115 65 15 53 20 35 23 20 20
Max 10000 10000
Min 135 75 18 60 25 40 28 25 25
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tCWD tRWD tAWD Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note 23)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns ns ns ns ns ns ns
(Note 24) (Note 24) (Note 24)
Min 138 94 49 94 49 37 82 52
Max 10000 10000
Min 166 112 62 112 62 47 97 62
Max 10000 10000
8
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W)
Limits Symbol tHPC tHPRWC tRAS tCPRH tCPWD tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time Hyper Page Mode read write / read modify write cycle time RAS low pulse width for read or write cycle RAS hold time after CAS precharge Delay time, CAS precharge to W low Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read (Note 26) (Note 27) (Note 24)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
(Note 25)
Unit ns ns ns ns ns ns ns ns ns ns ns
Min 30 71 82 38 55 37 52 55 20 35 38
Max
100000
Min 35 84 97 43 65 47 62 65 25 40 43
Max
100000
Test Mode Set Cycle
Limits Symbol tWSR tWHR Write setup time before RAS low Write hold time after RAS low Parameter
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Unit ns ns
Min 10 10
Max
Min 10 15
Max
9
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 32)
tRC tRAS VIH VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH A0 ~A9 VIL tRAH tASC tCAH
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
tRAL tCAL
tASR
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL tDZC VIH VIL tCAC tAA tCLZ DQ1~DQ4 (OUTPUTS) VOH VOL Hi-Z tRAC tDZO VIH VIL tORH tOEA tOCH OE Hi-Z tREZ tOHR
DATA VALID
tRRH tRCH
W
tCDD
DQ1~DQ4 (INPUTS)
tWEZ tOFF tOHC Hi-Z
tOEZ tODD
Note 32
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max)
Indicates the invalid output.
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH A0~A9 VIL tRAH
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
CAS
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tWCS W VIH VIL tDS VIH VIL
tWCH
tDH
DQ1~DQ4 (INPUTS)
DATA VALID
DQ1~DQ4 (OUTPUTS)
VOH VOL
Hi-Z
OE
VIH VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Delayed Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASR
ROW ADDRESS
tRP
RAS
tCRP tRSH tCAS
tRCD
CAS
VIH A0~A9 VIL
ROW ADDRESS
COLUMN ADDRESS
tCWL tRCS W VIH VIL tWCH tDZC DQ1~DQ4 (INPUTS) VIH VIL tCLZ Hi-Z tDS tDH
DATA VALID
tRWL tWP
DQ1~DQ4 (OUTPUTS)
VOH VOL
Hi-Z tOEH
Hi-Z
tDZO
tOEZ tODD
VIH OE VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tCRP tRP
VIH A0~A9 VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH W VIL
tAWD tCWD tRWD
tCWL tRWL tWP
tDS tDZC DQ1~DQ4 (INPUTS) VIH VIL tCAC tAA tCLZ DQ1~DQ4 (OUTPUTS) VOH VOL Hi-Z tRAC tDZO VIH VIL tOEA tOEZ OE
DATA VALID
tDH
Hi-Z
DATA VALID
Hi-Z tODD tOEH
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH
ROW ADDRESS
tRP
tRCD
tCAS
tCP
tHPC tCAS
tCP
tRSH tCAS
tASC
tCAH
tASC
tCAH
tASC
tCPRH tCAH
tASR
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH W VIL tCAL
tRAL tCAL
tRRH tRCH
tWEZ tDZC tRDD tCDD Hi-Z tCAC tAA tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL Hi-Z tRAC tDZO VIH OE VIL tODD
DATA VALID-1
DQ1~DQ4 (INPUTS)
VIH VIL tCAC tAA tDOH
tCAC tAA tDOH
DATA VALID-2
tREZ tOHR tOFF tOHC
DATA VALID-3
tCPA tOEA tOCH
tCPA tOEZ
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR VIH VIL tRAH tASC tCAH tASC tCAL tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tCRP
tASR
A0~A9
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tWCS VIH W VIL tDS VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
tDH
tDS
tDH
DQ1~DQ4 (INPUTS)
DATA VALID-1
DATA VALID-2
DATA VALID-3
VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH CAS VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tHPRWC tCAS
tRP
RAS
tRWL tCRP
tASR
ROW ADDRESS
A0~A9
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH W VIL tRWD tDZC DQ1~DQ4 (INPUTS) VIH VIL
Hi-Z
tAWD tCWL tWP tRCS tCWD tWP
tCWD
tCPWD tDS tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ
tCAC tAA tCLZ
DATA VALID-1
DQ1~DQ4 (OUTPUTS) VOL
VOH
Hi-Z
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ
tCPA tDZO
tODD tOEH tOEZ tOEA
VIH OE VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH VIL tRAH
ROW ADDRESS
tRP tRWL tCRP
tRCD
tCAS
tCP
tHPC tCAS
tCP
tHPRWC tCAS tCWL
tASC
tCAH
tASC
tCAH
tASC
tCAH
tASR
A0~A9
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL W VIH VIL tDZC DQ1~DQ4 (INPUTS) VIH VIL tCAC tAA tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z
tWCS
tWCH tCAL
tCPWD tAWD tCWD
tWP
tDS
tDH
tDZC
tDS
tDH
DATA VALID-2
tAA tCAC
DATA VALID-3
tWEZ
DATA VALID-1
tCLZ
DATA VALID-3
tRAC tDZO
tOEA tOCH tOEZ tDZO
tCPA tOEA tOEZ tOEH
VIH OE VIL tODD tODD
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH RAS VIL
VIH CAS VIL tCP tASC A0~A9 VIH
COLUMN-1 COLUMN-2 COLUMN-3
tCAS tCAH
tASC
tCAS tCAH
tASC
tCAH
VIL tCAL tRCH tWCS W VIH VIL tHPWD DQ1~DQ4 (INPUTS) VIH VIL tAA tCPA VOH DQ1~DQ4 (OUTPUTS) VOL tHCOD tHAOD tHPOD OE VIH VIL
Hi-Z
tCAL tWCH
tHCWD tHAWD tDS tDH tDZC
DATA VALID-2 Hi-Z
tCAC tWEZ
Hi-Z
tCAC tAA tCPA tCLZ
DATA VALID-1
DATA VALID-3
tDZC tOEZ tODD
tOEA
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH VIL tRAH
ROW ADDRESS
tRP
tHPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
tCRP
tASC
tCAH
tASC
tCAH
tASC
tCPRH tCAH
tASR
A0~A9
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS
tRRH tRCH
VIH W VIL tWEZ tDZC DQ1~DQ4 (INPUTS) VIH VIL tCAC tAA tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z DATA VALID-1
tRDD tCDD
Hi-Z
tCAC tAA tDOH
DATA VALID-1 DATA VALID-2
tCAC tAA tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO
tOEA
tOEZ tOCH tOEA
tCPA tCHOL
tCPA tOEZ tOEZ
VIH OE VIL
tOEPE
tOEPE
tODD
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tCRP
tASR
A0~A9
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS VIH VIL tRCH tRCS W
tRRH tRCH
tWEZ tDZC DQ1~DQ4 (INPUTS) VIH VIL tCAC tAA tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z DATA VALID-1
tWPE tRDD tCDD
Hi-Z
tCAC tAA tDOH tWEZ
DATA VALID-2
tCAC tAA tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH OE VIL
tCPA tOEA tOCH
tCPA tOEZ
tODD
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH VIL tCRP VIH CAS VIL tASR tRAH tASR tRPC tCRP tRP
A0~A9
VIH VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
DQ1~DQ4 (INPUTS)
VIH VIL
VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle*
tRC tRP RAS VIH VIL tRAS tRAS
tRC tRP
tRPC tCSR CAS VIH VIL tCPN
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tASR A0~A9 VIH VIL tRRH tRCH tRSR W VIH VIL tRHR tRSR tRHR tRCS
ROW ADDRESS COLUMN ADDRESS
DQ1~DQ4 (INPUTS)
VIH VIL tREZ tOHR tOFF tOHC
VOH DQ1~DQ4 (OUTPUTS) VOL
Hi-Z
tOEZ OE VIH VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 33)
tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS
tRAL
tRRH tRCH
VIH W VIL tDZC tCDD tRDD DQ1~DQ4 (INPUTS) VIH VIL tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
tREZ tOHR tOFF tOHC
Hi-Z
DQ1~DQ4 (OUTPUTS) VOL
VOH
tRAC tDZO VIH OE VIL
tOEA tORH
tOEZ tODD
Note 33: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Self Refresh Cycle* (Note 30)
tRP VIH RAS VIL
tRASS
tRPS
tRPC tRPC VIH CAS VIL tCPN tASR A0~A9 VIH VIL tRRH tRCH W VIH VIL tRDD tCDD DQ1~DQ4 (INPUTS) VIH VIL tREZ tOHR tOFF tOHC DQ1~DQ4 VOH (OUTPUTS) VOL tOEZ tODD VIH OE VIL
Hi-Z Hi-Z ROW ADDRESS
tCRP tCSR tCHS
tRSR
tRHR
tRCS
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Test Mode Set Cycle (Note 34)
tRC tRP RAS VIH VIL tRPC VIH VIL tCPN tASR VIH A0~A9 VIL tRCH VIH W VIL tWSR tWHR
ROW ADDRESS COLUMN ADDRESS
tRAS
tRP
tCSR
tCHR
tRPC
tCRP
CAS
tRCS
DQ1~DQ4 (INPUTS)
VIH VIL tOFF
DQ1~DQ4 VOH (OUTPUTS) VOL tOEZ
Hi-Z
VIH OE VIL
Note 34: The cycle is also avaiilable for initialization cycle, but in this case device enters test mode. The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram. The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle. During the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each DQ (input / output) port. No addressing of A0, A1(column only) is required. During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written independently for each DQ port. During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state if any bits differ. During the test mode operation, a WCBR cycle is used to perform refresh.
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width(tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read / Write operation (A) Timing Diagram
Read / Write Cycle Self Refresh Cycle Read / Write Cycle
tNSD RAS
tRASS100s
tSND
last refresh Cycle
first refresh cycle
Table 2
Read / Write Cycle CBR distributed refresh RAS only distributed refresh Read / Write Self Refresh tNSD125s tNSD16s Self Refresh Read / Write tSND125s tSND16s
(B) Definition of distributed refresh tREF tREF/1024 tREF/1024
RAS
refresh cycle
read/write cycles
refresh cycle
refresh cycle
read/write cycles
Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 1024 constant period(125s max.) CBR cycles within 128 ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A9) are selected during 1024 constant period(16s max.) RAS only refresh cycles within 16.4 ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND(shown in table 2). 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16s. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16s.
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation (A) Timing diagram
Read / Write
Self Refresh
Read / Write
tNSB
tRASS100s
tSNB
RAS
first refresh cycles
refresh cycles 1024 cycles
refresh cycles 1024 cycles
last refresh Cycles
Table 3
Read / Write Cycle CBR burst refresh RAS only burst refresh Read / Write Self Refresh tNSB16.4ms Self Refresh Read / Write tSNB16.4ms
tNSB+tSNB16.4ms
(B) Definition of burst refresh
16.4ms
RAS
refresh cycles 1024cycles read/write cycles
Definition of CBR burst refresh The CBR burst refresh performs more than 1024 continuous CBR cycles within 16.4 ms. Definition of RAS only burst refresh All combination of nine row address signals (A0 ~A9) are selected during 1024 continuous RAS only refresh cycles within 16.4 ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval ns from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4 ms. Switching from self refresh operation to read/write operation. The time interval snob from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 16.4 ms. 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB(Shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB(shown in table 3).

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